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APL5325
Adjustable Low Dropout 300mA Linear Regulator
Features
* * * * * * * * *
Wide Operating Voltage: 3~6V Low Dropout Voltage: 300mV(Typical) @ 300mA Guaranteed 300mA Output Current Adjustable Output Voltage: 0.8~5.5V Current-Limit Protection with Foldback Current Over-Temperature Protection Stable with Low ESR Ceramic Capacitor SOT-23-5 Package Lead Free and Green Devices Available (RoHS Compliant)
General Description
The APL5325 is a P-channel low dropout linear regulator which needs only one input voltage from 3 to 6V, and delivers current up to 300mA to set output voltage. It also can work with low ESR ceramic capacitors and is ideal for using in the battery-powered applications such as notebook computers and cellular phones. Typical dropout voltage is only 300mV at 300mA loading. Current limit with current foldback and thermal shutdown functions protect the device against current over-loads and over temperature. The APL5325 is available in a SOT23-5 package.
Pin Configuration
Applications
* * *
Cellular Phones
SHDN 1 GND 2 VIN 3 SOT-23-5
5 SET 4 VOUT
Portable and Battery-Powered Equipment Notebook and Personal Computers
Simplified Application Circuit
APL5325
VIN CIN 3 1 VIN VOUT 4
VOUT COUT
SHDN SET 5 GND 2
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Nov., 2008 1 www.anpec.com.tw
APL5325
Ordering and Marking Information
APL5325 Assembly Material Handling Code Temperature Range Package Code Package Code B: SOT-23-5 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXXX - Date Code
APL5325
B:
25RX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Absolute Maximum Ratings
Symbol VIN VSHDN PD TJ TSTG TSDR VIN Supply Voltage (VIN to GND) SHDN Input Voltage (SHDN to GND) Power Dissipation Junction Temperature Storage Temperature
(Note 1)
Rating -0.3 ~ 6.5 -0.3 ~ 6.5 Internally Limited -40 ~ 150 -65 ~ 150 260 Unit V V W
o o o
Parameter
C
C C
Maximum Lead Soldering Temperature, 10 Seconds
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA JC Parameter Thermal Resistance-Junction to Ambient Thermal Resistance-Junction to Case SOT-23-5
(Note 2)
Typical Value SOT-23-5 240 130
Unit
o
C/W C/W
o
Note 2 : JA is measured with the component mounted on a high effective thermal conductivity test board in free air.
Recommended Operating Conditions
Symbol VIN VOUT IOUT CIN COUT TJ VIN Supply Voltage Output Voltage VOUT Output Current Input Capacitor Output Capacitor Junction Temperature
2
Parameter
Range 3~6 0.8 ~ 5.5 0 ~ 300 0.22 ~ 100 1.5 ~ 100 -40 ~ 125
Unit V V mA F F
o
C
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Nov., 2008
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APL5325
Electrical Characteristics
Unless otherwise specified, these specifications apply over VIN = VOUT+1V, IOUT=0~300mA, CIN = 1F, COUT = 2.2F, TA = -40 to 85oC. Typical values are at TA = 25oC.
Symbol VIN VOUT IQ VREF Input Voltage
Parameter
Test Conditions Min. 3 0.8 IOUT =10mA ~300mA Measured on SET, VIN=3V, IOUT=10mA IOUT=10mA VOUT%/VIN, IOUT=10mA VOUT%/IOUT VOUT = 2.5V, IOUT = 300mA VOUT = 3.3V, IOUT = 300mA -2 -0.06 -0.2 450 VOUT = 0V 1.6 SHDN = Low SHDN = Low, VIN = 6V VSET=0.8V -100
APL5325 Typ. 135 0.8 500 300 45 160 550 80 60 0.1 3 160 40 Max. 6 5.5 160 +2 +0.06 +0.2 650
Unit V V A V % %/V %/A mV 400 V 0.4 1 100 A M
o o
Output Voltage Range Quiescent Current Reference Voltage Output Voltage Accuracy
REGLINE
Line Regulation
REGLOAD Load Regulation VDROP Dropout Voltage
PSRR
Power Supply Ripple Rejection Ratio Noise
f = 10kHz, IOUT = 300mA f = 80Hz to 100kHz, IOUT = 300mA
dB VRMS mA mA
ILIMIT ISHORT
Current Limit Foldback Current SHDN Input Voltage High SHDN Input Voltage Low VOUT Discharge MOSFET RDS(ON) Shutdown VIN Supply Current SHDN Pull Low Resistance Over Temperature Threshold Over Temperature Hysteresis SET Input Bias Current
C C
nA
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APL5325
Typical Operating Characteristics
Quiescent Current vs. Supply Voltage
160 140 Quiescent Current, IQ (A) 120 100 80 60 40 20 0 0 1 2 3 4 5 6 7 Supply Voltage, V IN (V)
126 -50 -25 0 25 50 75 100 125
Quiescent Current vs. Junction Temperature
138
IOUT= 0mV
Quiescent Current, IQ (A)
136 134 132 130 128
Junction Temperature, T J (o C)
PSRR vs. Frequency
0
Dropout Voltage vs. Output Current
400
Dropout Voltage, VDROP(mV)
-10 -20
VIN=3.3V, VOUT=1.2V, COUT=2.2F,IOUT=300mA
350 300 250 200 150 100 50 0
VOUT=3.3V
o TJ=125oC TJ=75 C
PSRR(dB)
-30 -40 -50 -60 -70 -80 1000 10000 100000
TJ=-50oC TJ=25oC
0
100
200
300
Frequency(Hz)
Output Current, I OUT(mA)
Dropout Voltage vs. Output Current
700 Dropout Voltage, VDROP(mV) 600 500 400 300 200 100 0 0 100 200 300 Output Current, IOUT(mA)
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TJ=-50 C TJ=25oC
o
Current Limit vs. Junction Temperature
600
VIN=5V Current Limit, ILIMIT(mA)
VOUT=2.5V TJ=125oC TJ=75oC
550
500
VIN=3.3V
450
400 -50
-25
0
25
50
75
100
125
Junction Temperature,
T J(oC)
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APL5325
Typical Operating Characteristics (Cont.)
Loop Gain vs. Frequency
50 40 30 Loop Gain (dB) 20 10 0 -10 -20 -30 -40 1000 10000 100000 1000000 IOUT=300mA
160
Phase vs. Frequency
140 VIN=3.3V, VOUT=1.2V, CIN=1F, COUT=2.2F IOUT=300mA
VIN=3.3V, VOUT=1.2V, CIN=1F, COUT=2.2F IOUT=100mA
Phase (degree)
120 100 80 60 40 20 0 1000 10000
IOUT=100mA
100000
1000000
Frequency (Hz)
Frequency (Hz)
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APL5325
Operating Waveforms
Enable
Shutdown
CH1
SHDN VIN
SHDN CH1 VIN CH2
CH2 CH3 VOUT
CH3
VOUT
IOUT CH4
CH4
I OUT
CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 200s/div
CH1 : SHDN , 5V/div CH2 : VIN , 5V/div CH3 : VOUT , 2V/div CH4 : IOUT , 100mA/div Time : 10s/div
Load Transient
V IN=5V ; C I N=1F ; C OUT =2.2F ; T R =1s CH1
Line Transient
C IN=1 F ; C OUT =2.2F ; T R =5s ; I OUT =10mA V IN
VOUT
I OUT
VOUT CH2
CH2
CH1
CH1 : VOUT , 50mV/div AC CH2 : IOUT , 100mA/div Time : 20s/div
CH1 : VIN , 1V/div DC CH2 : VOUT , 50mV/div AC Time : 20s/div
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APL5325
Operating Waveforms (Cont.)
Power On
Power Off
VIN CH1 VOUT CH2 I OUT
CH1
VIN
CH2
VOUT
CH3
CH3
IOUT
CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 2ms/div
CH1 : VIN , 2V/div CH2 : VOUT , 2V/div CH3 : IOUT , 100mA/div Time : 10ms/div
Pin Description
PIN NO. 1 2 3 4 5 NAME SHDN GND VIN VOUT SET FUNCTION Shutdown control pin, logic high: enable; logic low: shutdown. Ground pin. Voltage supply input pin. Regulator output pin. Connect this pin to an external resistor divider to adjust output voltage.
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APL5325
Block Diagram
UVLO & Shutdown Logic
SHDN
VIN
Thermal Shutdown 0.8V 3M
+
Foldback Current Limit
VOUT
SET GND
Typical Application Circuit
VIN
3 1
VIN SHDN GND 2
VOUT SET
4 5 R1
VOUT
CIN 1F
COUT 2.2F
Enable
R2
Shutdown
R1 VOUT = 0.8 1 + R2
Designation CIN CIN COUT COUT
Supplier Murata Murata Murata Murata
Part Number GRM185R61A105KE36 GRM188R71A105KA61 GRM188R61A225KE34 GRM188R71A225KE15
Specification 0603, X5R, 10V, 1F 0603, X7R, 10V, 1F 0603, X5R, 10V, 2.2F 0603, X7R, 10V, 2.2F
Reference: www.murata.com
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APL5325
Function Description
Output Voltage Regulation The APL5325 is an adjustable low dropout linear regulator. The output voltage set by the resistor-divider is determined by:
R1 VOUT = 0.8 1 + R2
Where R1 is connected from VOUT to SET with Kelvin sensing and R2 is connected from SET to GND. The recommended value of R2 is in the range of 100 to100k. An error amplifier works with a temperature compensated 0.8V reference and an output PMOS regulates the output to the presetting voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output PMOS which provides load current from VIN to VOUT. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of APL5325. When the junction temperature exceeds +160C, a thermal sensor turns off the output PMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start cycle after the junction temperature is cooled down by 40oC. The thermal shutdown is designed with a 40oC hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, device power dissipation should be externally limited so that junction temperature will not exceed 125oC. Shutdown Control The APL5325 has an active-low shutdown function. Force SHDN high (>1.6V) enables the VOUT; force SHDN low (<0.4V) disables the VOUT. SHDN is internally pulled low by a resistor (3m typical). If it is not used, connect to VIN for normal operation.
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APL5325
Application Information
Input Capacitor The APL5325 requires proper input capacitors to supply surge current during stepping load transients to prevent the input rail from dropping . Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN limit the slew rate of the surge current, place the Input capacitors near VIN as close as possible. Input capacitors should be larger than 1F and a minimum ceramic capacitor of 1F is necessary. Output Capacitor The APL5325 needs a proper output capacitor to maintain circuit stability and to improve transient response over temperature and current. In order to insure the circuit stability, the proper output capacitor value should be larger than 2.2F. With X5R and X7R dielectrics, 2.2F is sufficient at all operating temperatures. Large output capacitor value can reduce noise and improve load-transient response and PSRR, however, it also affects power on issue. Equation (1) shows the relationship between the maximum COUT value and the VOUT.
C OUT(max) = 101 - 19.5 VOUT
Operation Region and Power Dissipation The APL5325 maximum power dissipation depends on the thermal resistance and temperature difference between the die junction and ambient air. The power dissipation PD across the device is: PD = (TJ - TA) / cJA where (TJ-TA) is the temperature difference between the junction and ambient air. c JA is the thermal resistance between Junction and ambient air. Assuming the TA=25 oC and maximum TJ=160 oC (typical thermal limit threshold), the maximum power dissipation is calculated as: PD(max)=(160-25)/240 = 0.56(W) For normal operation, do not exceed the maximum junction temperature rating of TJ = 125 oC. The calculated power dissipation should less than: PD =(125-25)/240 = 0.41(W) The GND provides an electrical connection to the ground and channels heat away. Connect the GND to the ground by using a large pad or a ground plane. Layout Consideration Figure 2 illustrates the layout. Below is a checklist for your layout: 1. Please place the input capacitors close to the VIN. 2. Ceramic capacitors for load must be placed near the load as close as possible. 3. To place APL5325 and output capacitors near the load is good for performance. 4. Large current paths, the bold lines in figure 2, must have wide tracks. 5. Divider resistor R1 and R2 must be placed near the SET as close as possible.
Where the unit of COUT is F and VOUT is V. Figure 1 shows the curve of maximum output capacitor over the output voltage. The output voltage range is from 0.8 to 5.5V and the output capacitor value should under the line. Output capacitors must be placed at the load and the ground pin as close as possible and the impedance of the layout must be minimized.
120
Output Capacitor (F)
110 100 90 80 70 60 0 1 2 3 4 5 6
Output Voltage (V)
Figure 1
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APL5325
Application Information (Cont.)
Layout Consideration (Cont.)
CIN APL5325 VIN VOUT SET GND 2 R2 LOAD 3 4 5 R1 VOUT VIN
COUT
Figure 2 Recommended Minimum Footprint SOT-23-5
0.076
0.1
0.038
0.02 Unit : Inch
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APL5325
Package Information
SOT-23-5
D e
SEE VIEW A
E1
b e1
E
c
0.25
GAUGE PLANE SEATING PLANE VIEW A SOT-23-5 INCHES MIN. MAX. 0.057 0.000 0.035 0.012 0.003 0.106 0.102 0.055 0.037 BSC 0.075 BSC 0.60 8 0.012 0 0.024 8 0.006 0.051 0.020 0.009 0.122 0.118 0.071 MAX. 1.45 0.15 1.30 0.50 0.22 3.10 3.00 1.80
A2 A1
A
S Y M B O L A A1 A2 b c D E E1 e e1 L 0
MILLIMETERS MIN.
0.00 0.90 0.30 0.08 2.70 2.60 1.40 0.95 BSC 1.90 BSC 0.30 0
Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side.
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0
L
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APL5325
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A 178.0O .00 2
H 50 MIN. P1 4.0O .10 0
H A
T1
T1 8.4+2.00 -0.00 P2 2.0O .05 0
C 13.0+0.50 -0.20 D0 1.5+0.10 -0.00
d 1.5 MIN. D1 1.0 MIN.
D 20.2 MIN. T 0.6+0.00 -0.40
W 8.0O .30 0 A0 3.20O .20 0
W
E1 1.75O .10 0 B0 3.10O .20 0
F 3.5O .05 0 K0 1.50O .20 0 (mm)
SOT-23-5
P0 4.0O .10 0
Devices Per Unit
Package Type SOT-23-5 Unit Tape & Reel Quantity 3000
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APL5325
Taping Direction Information
SOT-23-5
USER DIRECTION OF FEED
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
14
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
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APL5325
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm <350
3
Volume mm <350
3
Volume mm 350
3
240 +0/-5C 225 +0/-5C Volume mm 350-2000
3
225 +0/-5C 225 +0/-5C Volume mm >2000
3
Table 2. Pb-free Process - Package Classification Reflow Temperatures Package Thickness
<1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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